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? 2004 microchip technology inc. ds21210g-page 1 24aa024/24lc024/24AA025/24lc025 device selection table features ? single supply with operation from 1.8v to 5.5v low-power cmos technology - 1 ma active current typical -1 a standby current typical at 5.5v organized as a single block of 256 bytes (256 x 8) hardware write protection for entire array (24xx024) 2-wire serial interface bus, i 2 c? compatible 100 khz and 400 khz clock compatibility page write buffer for up to 16 bytes self-timed write cycle (including auto-erase) 10 ms max. write cycle time address lines allow up to eight devices on bus 1,000,000 erase/write cycles esd protection > 4,000v data retention > 200 years 8-pin pdip, soic, tssop and msop packages available for extended temperature ranges - industrial (i): -40c to +85c pin function table description the microchip technology inc. 24aa024/24lc024/ 24AA025/24lc025 is a 2 kbit serial electrically erasable prom with a voltage range of 1.8v to 5.5v. the device is organized as a single block of 256 x 8-bit memory with a 2-wire serial interface. low current design permits operation with typical standby and active currents of only 1 a and 1 ma, respectively. the device has a page write capability for up to 16 bytes of data. functional address lines allow the connection of up to eight 24aa024/24lc024/ 24AA025/24lc025 devices on the same bus for up to 16k bits of contiguous eeprom memory. the device is available in the standard 8-pin pdip, 8-pin soic (150 mil), tssop and msop packages. package types block diagram part number v cc range max clock temp. range write protect 24aa024 1.8v - 5.5v 400 khz (1) iyes 24AA025 1.8v - 5.5v 400 khz (1) ino 24lc024 2.5v - 5.5v 400 khz i yes 24lc025 2.5v - 5.5v 400 khz i no note 1: 100 khz for v cc < 2.5v name function v ss ground sda serial data scl serial clock v cc 1.8v to 5.5v power supply a0, a1, a2 chip selects wp hardware write-protect (24lc024) note: *wp pin available only on 24xx024. this pin has no internal connection on 24xx025. pdip/soic tssop/msop a0 a1 a2 v ss v cc wp* scl sda 24xx024 24xx025 1 2 3 4 8 7 6 5 a0 a1 a2 v ss v cc wp* scl sda 1 2 3 4 8 7 6 5 24xx024 24xx025 i/o control logic memory control logic xdec hv generator eeprom array write-protect circuitry ydec v cc v ss sense amp. r/w control sda scl a0 a1 a2 wp* 2k i 2 c ? serial eeprom
24aa024/24lc024/24AA025/24lc025 ds21210g-page 2 ? 2004 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc ............................................................................................................................... ..............................................6.5v all inputs and outputs w.r.t. v ss ......................................................................................................... -0.6v to v cc +1.0v storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature with power applied ......................................................................................... .......-40c to +125c esd protection on all pins ............................................................................................................................... ....................... 4 kv ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 1-1: dc characteristics all parameters apply across the specified operating ranges unless otherwise noted. v cc = 1.8v to 5.5v industrial (i): t a = -40c to +85c parameter symbol min. max. units conditions scl and sda pins: high-level input voltage v ih 0.7 v cc ?v? low-level input voltage v il ? 0.3 v cc v? hysteresis of schmitt trigger inputs v hys 0.05 v cc ?v (note) low-level output voltage v ol ?0.40vi ol = 3.0 ma, v cc = 4.5v i ol = 2.1 ma, v cc = 2.5v input leakage current i li ?1 av in = 0.1v to 5.5v, wp = v ss output leakage current i lo ?1 av out = 0.1v to 5.5v pin capacitance (all inputs/outputs) c in , c out ?10pfv cc = 5.0v (note) t a = 25c, f = 1 mhz operating current i cc read ? 1 ma v cc = 5.5v, scl = 400 khz i cc write ? 3 ma v cc = 5.5v standby current i ccs ?1 av cc = 5.5v, sda = scl = v cc wp = v ss , a0, a1, a2 = v ss note: this parameter is periodically sampled and not 100% tested.
? 2004 microchip technology inc. ds21210g-page 3 24aa024/24lc024/24AA025/24lc025 table 1-2: ac characteristics figure 1-1: bus timing data all parameters apply across the specified operating ranges unless otherwise noted. v cc = 1.8v to 5.5v industrial (i): t a = -40c to +85c parameter symbol std mode vcc = 2.5v - 5.5v fast mode units remarks min. max. min. max. clock frequency f clk ? 100 ? 400 khz ? clock high time t high 4000 ? 600 ? ns ? clock low time t low 4700 ? 1300 ? ns ? sda and scl rise time t r ? 1000 ? 300 ns (note 1) sda and scl fall time t f ? 300 ? 300 ns (note 1) start condition hold time t hd : sta 4000 ? 600 ? ns after this period the first clock pulse is generated start condition setup time t su : sta 4700 ? 600 ? ns only relevant for repeated start condition data input hold time t hd : dat 0? 0?ns (note 2) data input setup time t su : dat 250 ? 100 ? ns ? stop condition setup time t su : sto 4000 ? 600 ? ns ? output valid from clock t aa ? 3500 ? 900 ns (note 2) bus free time t buf 4700 ? 1300 ? ns time the bus must be free before a new transmission can start output fall time from v ih minimum to v il maximum t of ? 250 20 +0.1 c b 250 ns (note 1) , c b 100 pf input filter spike suppression (sda and scl pins) t sp ? 50 ? 50 ns (note 3) write-cycle time t wc ? 10 ? 10 ms byte or page mode endurance 1m ? 1m ? cycles 25c, (note 4) note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to schmitt trigger inputs which provide improved noise spike suppression. this eliminates the need for a ti specification for standard operation. 4: this parameter is not tested but ensured by characterization. for endurance estimates in a specific application, please consult the total endurance? model which can be downloaded at www.microchip.com. scl sda in t su : sta sda out t hd : sta t low t high t r t buf t aa t hd : dat t su : dat t su : sto t sp t f
24aa024/24lc024/24AA025/24lc025 ds21210g-page 4 ? 2004 microchip technology inc. 2.0 pin descriptions 2.1 sda serial data sda is a bidirectional pin used to transfer addresses and data into and out of the device. it is an open-drain terminal, therefore the sda bus requires a pull-up resistor to v cc (typical 10 k ? for 100 khz, 2 k ? for 400 khz). for normal data transfer, sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop conditions. 2.2 scl serial clock the scl input is used to synchronize the data transfer from and to the device. 2.3 a0, a1, a2 the levels on the a0, a1 and a2 inputs are compared with the corresponding bits in the slave address. the chip is selected if the compare is true. up to eight 24aa024/24lc024/24AA025/24lc025 devices may be connected to the same bus by using different chip select bit combinations. these inputs must be connected to either v cc or v ss . 2.4 wp (24xx024 only) wp is the hardware write-protect pin. it must be tied to v cc or v ss . if tied to vcc, hardware write protection is enabled. if wp is tied to vss, the hardware write protection is disabled. note that the wp pin is available only on the 24xx024. this pin is not internally connected on the 24lc025. 2.5 noise protection the 24aa024/24lc024/24AA025/24lc025 employs a v cc threshold detector circuit which disables the inter- nal erase/write logic if the v cc is below 1.5 volts at nominal conditions. the scl and sda inputs have schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation, even on a noisy bus. 3.0 functional description the 24aa024/24lc024/24AA025/24lc025 supports a bidirectional, 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as transmitter, while a device receiving data is defined as receiver. the bus has to be controlled by a master device which generates the serial clock (scl), controls the bus access and generates the start and stop conditions, while the 24aa024/ 24lc024/24AA025/24lc025 works as slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated.
? 2004 microchip technology inc. ds21210g-page 5 24aa024/24lc024/24AA025/24lc025 4.0 bus characteristics the following bus protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (figure 4-1). 4.1 bus not busy (a) both data and clock lines remain high. 4.2 start data transfer (b) a high-to-low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 4.3 stop data transfer (c) a low-to-high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 4.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one bit of data per clock pulse. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device and is, theoretically, unlimited, (though only the last sixteen will be stored when performing a write operation). when an overwrite does occur, it will replace data in a first-in first-out fashion. 4.5 acknowledge each receiving device, when addressed, is required to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge-related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition (figure 4-2). figure 4-1: data transfer sequence on the serial bus characteristics figure 4-2: acknowledge timing note: the 24aa024/24lc024/24AA025/ 24lc025 does not generate any acknowledge bits if an internal programming cycle is in progress. (a) (b) (c) (d) (a ) (c) scl sda start condition address or acknowledge valid data allowed to change stop condition scl 9 8 7 6 5 4 3 2 1 123 transmitter must release the sda line at this point allowing the receiver to pull the sda line low to acknowledge the previous eight bits of data. receiver must release the sda line at this point so the transmitter can continue sending data. sda acknowledge bit data from transmitter data from transmitter
24aa024/24lc024/24AA025/24lc025 ds21210g-page 6 ? 2004 microchip technology inc. 5.0 device addressing a control byte is the first byte received following the start condition from the master device (figure 5-1). the control byte consists of a four-bit control code. for the 24aa024/24lc024/24AA025/24lc025, this is set as ? 1010 ? binary for read and write operations. the next three bits of the control byte are the chip select bits (a2, a1, a0). the chip select bits allow the use of up to eight 24aa024/24lc024/24AA025/24lc025 devices on the same bus and are used to select which device is accessed. the chip select bits in the control byte must correspond to the logic levels on the corre- sponding a2, a1 and a0 pins for the device to respond. these bits are in effect the three most significant bits of the word address. the last bit of the control byte defines the operation to be performed. when set to a one, a read operation is selected. when set to a zero, a write operation is selected. following the start condition, the 24aa024/ 24lc024/24AA025/24lc025 monitors the sda bus checking the control byte being transmitted. upon receiving a ? 1010 ? code and appropriate chip select bits, the slave device outputs an acknowledge signal on the sda line. depending on the state of the r/w bit, the 24aa024/24lc024/24AA025/24lc025 will select a read or write operation. figure 5-1: control byte format 5.1 contiguous addressing across multiple devices the chip select bits a2, a1 and a0 can be used to expand the contiguous address space for up to 16k bits by adding up to eight 24aa024/24lc024/24AA025/ 24lc025 devices on the same bus. in this case, soft- ware can use a0 of the control byte as address bit a8, a1 as address bit a9 and a2 as address bit a10. it is not possible to sequentially read across device boundaries. 1 0 1 0 a2 a1 a0 sack r/w control code chip select bits slave address acknowledge bit start bit read/write bit
? 2004 microchip technology inc. ds21210g-page 7 24aa024/24lc024/24AA025/24lc025 6.0 write operations 6.1 byte write following the start signal from the master, the device code(4 bits), the chip select bits (3 bits) and the r/w bit (which is a logic-low) is placed onto the bus by the master transmitter. the device will acknowledge this control byte during the ninth clock pulse. the next byte transmitted by the master is the word address and will be written into the address pointer of the 24aa024/ 24lc024/24AA025/24lc025. after receiving another acknowledge signal from the 24aa024/24lc024/ 24AA025/24lc025, the master device will transmit the data word to be written into the addressed memory location. the 24aa024/24lc024/24AA025/24lc025 acknowledges again and the master generates a stop condition. this initiates the internal write cycle and, dur- ing this time, the 24aa024/24lc024/24AA025/ 24lc025 will not generate acknowledge signals (figure 6-1). if an attempt is made to write to the protected portion of the array when the hardware write protection (24xx024 only) has been enabled, the device will acknowledge the command but no data will be written. the write cycle time must be observed even if write protection is enabled. 6.2 page write the write control byte, word address and the first data byte are transmitted to the 24aa024/24lc024/ 24AA025/24lc025 in the same way as in a byte write. however, instead of generating a stop condition, the master transmits up to 15 additional data bytes to the 24aa024/24lc024/24AA025/24lc025, which are temporarily stored in the on-chip page buffer and will be written into the memory once the master has transmit- ted a stop condition. upon receipt of each word, the four lower-order address pointer bits are internally incremented by one. the higher-order four bits of the word address remain constant. if the master should transmit more than 16 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte-write operation, once the stop condition is received, an internal write cycle will begin (figure 6-2). if an attempt is made to write to the protected portion of the array when the hardware write protection has been enabled, the device will acknowledge the command but no data will be written. the write cycle time must be observed even if write protection is enabled. 6.3 write protection the wp pin (available on 24xx024 only) must be tied to v cc or v ss . if tied to v cc , the entire array will be write-protected. if the wp pin is tied to v ss , write operations to all address locations are allowed. figure 6-1: byte write figure 6-2: page write note: page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page buffer size (or ?page size?) and end at addresses that are integer multiples of [page size - 1]. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. it is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. s p bus activity master sda line bus activity s t a r t s t o p control byte word address data a c k a c k a c k s p bus activity master sda line bus activity s t a r t control byte word address (n) data (n) data (n + 15) s t o p a c k a c k a c k a c k a c k data (n +1)
24aa024/24lc024/24AA025/24lc025 ds21210g-page 8 ? 2004 microchip technology inc. 7.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write command has been issued from the master, the device initiates the internally-timed write cycle, with ack polling being initiated immediately. this involves the master sending a start condition followed by the control byte for a write command (r/w = 0 ). if the device is still busy with the write cycle, no ack will be returned. if no ack is returned, the start bit and control byte must be re-sent. if the cycle is complete, the device will return the ack and the master can then proceed with the next read or write command. see figure 7-1 for a flow diagram of this operation. figure 7-1: acknowledge polling flow send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0)? next operation no yes
? 2004 microchip technology inc. ds21210g-page 9 24aa024/24lc024/24AA025/24lc025 8.0 read operations read operations are initiated in the same way as write operations, with the exception that the r/w bit of the slave address is set to ? 1 ?. there are three basic types of read operations: current address read, random read and sequential read. 8.1 current address read the 24aa024/24lc024/24AA025/24lc025 contains an address counter that maintains the address of the last word accessed, internally incremented by one. therefore, if the previous read access was to address n, the next current address read operation would access data from address n + 1. upon receipt of the slave address with the r/w bit set to ? 1 ?, the 24aa024/ 24lc024/24AA025/24lc025 issues an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer but does generate a stop condition and the 24aa024/24lc024/24AA025/ 24lc025 discontinues transmission (figure 8-1). 8.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, the word address must first be set. this is accomplished by sending the word address to the 24aa024/24lc024/24AA025/24lc025 as part of a write operation. once the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. the master then issues the control byte again, but with the r/w bit set to a ? 1 ?. the 24aa024/24lc024/24AA025/ 24lc025 will then issue an acknowledge and transmits the eight bit data word. the master will not acknowl- edge the transfer but does generate a stop condition and the 24aa024/24lc024/24AA025/24lc025 dis- continues transmission (figure 8-2). after this com- mand, the internal address counter will point to the address location following the one that was just read. 8.3 sequential read sequential reads are initiated in the same way as a random read except that after the 24aa024/24lc024/ 24AA025/24lc025 transmits the first data byte, the master issues an acknowledge (as opposed to a stop condition in a random read). this directs the 24aa024/ 24lc024/24AA025/24lc025 to transmit the next sequentially-addressed 8-bit word (figure 8-3). to provide sequential reads, the 24aa024/24lc024/ 24AA025/24lc025 contains an internal address pointer that is incremented by one upon completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. the internal address pointer will automatically roll over from address 0ffh to address 000h. figure 8-1: current address read bus activity master sda line bus activity p s s t o p control byte s t a r t data a c k n o a c k n
24aa024/24lc024/24AA025/24lc025 ds21210g-page 10 ? 2004 microchip technology inc. figure 8-2: random read figure 8-3: sequential read sp s bus activity master sda line bus activity s t a r t s t o p control byte a c k word address (n) control byte s t a r t data (n) a c k a c k n o a c k bus activity master sda line bus activity control byte data (n) data (n + 1) data (n + 2) data (n + x) n o a c k a c k a c k a c k a c k s t o p p
? 2004 microchip technology inc. ds21210g-page 11 24aa024/24lc024/24AA025/24lc025 9.0 packaging information 9.1 package marking information xxxxxxxx t/xxxnnn yyww 8-lead pdip (300 mil) example: 8-lead soic (150 mil) example: 8-lead tssop example: 24lc024 i/p13f 0319 24lc024 i/sn0319 13f 8-lead msop example: xxxx tyww nnn xxxxt ywwnnn 4l24 i319 13f 4l24i 31913f legend: xx...x customer specific information* t temperature grade yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard otp marking consists of microchip part number, year code, week code, and traceability code. part number tssop marking code 24aa024 4a24 24lc024 l24 24AA025 4a25 24lc025 l25 xxxxxxxx t/xxyyww nnn part number msop marking code 24aa024 4a24i 24lc024 4l24i 24AA025 4a25i 24lc025 4l25i
24aa024/24lc024/24AA025/24lc025 ds21210g-page 12 ? 2004 microchip technology inc. 8-lead plastic dual in-line (p) ? 300 mil (pdip) b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches* millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed jedec equivalent: ms-001 drawing no. c04-018 .010? (0.254mm) per side. significant characteristic
? 2004 microchip technology inc. ds21210g-page 13 24aa024/24lc024/24AA025/24lc025 8-lead plastic small outline (sn) ? narrow, 150 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.62 0.48 .030 .025 .019 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 5.00 4.90 4.80 .197 .193 .189 d overall length 3.99 3.91 3.71 .157 .154 .146 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n p b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-057 significant characteristic
24aa024/24lc024/24AA025/24lc025 ds21210g-page 14 ? 2004 microchip technology inc. 8-lead plastic thin shrink small outline (st) ? 4.4 mm (tssop) 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.30 0.25 0.19 .012 .010 .007 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 0.70 0.60 0.50 .028 .024 .020 l foot length 3.10 3.00 2.90 .122 .118 .114 d molded package length 4.50 4.40 4.30 .177 .173 .169 e1 molded package width 6.50 6.38 6.25 .256 .251 .246 e overall width 0.15 0.10 0.05 .006 .004 .002 a1 standoff 0.95 0.90 0.85 .037 .035 .033 a2 molded package thickness 1.10 .043 a overall height 0.65 .026 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters* inches units a2 a a1 l c 1 2 d n p b e e1 foot angle 048048 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .005? (0.127mm) per side. jedec equivalent: mo-153 drawing no. c04-086 significant characteristic
? 2004 microchip technology inc. ds21210g-page 15 24aa024/24lc024/24AA025/24lc025 8-lead plastic micro small outline package (ms) (msop) d a a1 l c (f) a2 e1 e p b n 1 2 5 5 - - dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not .037 ref f footprint (reference) exceed .010" (0.254mm) per side. notes: drawing no. c04-111 *controlling parameter mold draft angle top mold draft angle bottom foot angle lead width lead thickness c b .003 .009 .006 .012 dimension limits overall height molded package thickness molded package width overall length foot length standoff overall width number of pins pitch a l e1 d a1 e a2 .016 .024 .118 bsc .118 bsc .000 .030 .193 typ. .033 min p n units .026 bsc nom 8 inches 0.95 ref - - .009 .016 0.08 0.22 0 0.23 0.40 8 millimeters* 0.65 bsc 0.85 3.00 bsc 3.00 bsc 0.60 4.90 bsc .043 .031 .037 .006 0.40 0.00 0.75 min max nom 1.10 0.80 0.15 0.95 max 8 -- - 15 5 - 15 5 - jedec equivalent: mo-187 0 - 8 5 5 - - 15 15 - - - -
24aa024/24lc024/24AA025/24lc025 ds21210g-page 16 ? 2004 microchip technology inc. appendix a: revision history revision f corrections to section 1.0, electrical characteristics. revision g added part number 24AA025 to document. correction to section 1.0, ambient temperature.
? 2004 microchip technology inc. ds21210g-page 17 24aa024/24lc024/24AA025/24lc025 on-line support microchip provides on-line support on the microchip world wide web site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape ? or microsoft ? internet explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available at the following url: www.microchip.com the file transfer site is available by using an ftp service to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development systems, technical information and more listing of seminars and events systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive the most current upgrade kits. the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-792-7302 for the rest of the world. 042003
24aa024/24lc024/24AA025/24lc025 ds21210g-page 18 ? 2004 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21210g 24aa024/24lc024/24AA025/24lc025 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2004 microchip technology inc. ds21210g-page 19 24aa024/24lc024/24AA025/24lc025 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. device: 24aa024: 1.8v, 2 kbit addressable serial eeprom with wp pin. 24aa024t:1.8v, 2 kbit addressable serial eeprom (tape and reel) with wp pin. 24lc024: 2.5v, 2 kbit addressable serial eeprom with wp pin. 24lc024t:2.5v, 2 kbit addressable serial eeprom (tape and reel) with wp pin. 24AA025: 1.8v, 2 kbit addressable serial eeprom with no wp pin. 24AA025t:1.8v, 2 kbit addressable serial eeprom (tape and reel) with no wp pin. 24lc025: 2.5v, 2 kbit addressable serial eeprom (tape and reel) with no wp pin. 24lc025t:2.5v, 2 kbit addressable serial eeprom (tape and reel) with no wp pin. temperature range: i = -40c to +85c package: p = plastic dip, (300 mil body), 8-lead sn = plastic soic, (150 mil body) st = tssop, 8-lead ms = msop, 8-lead part no. x /xx package temperature range device examples: a) 24aa024-i/p: industrial temperature, 1.8v, pdip package b) 24aa024-i/sn: industrial temperature, 1.8v, soic package c) 24AA025t-i/st: industrial temperature, 1.8v, tssop package, tape and reel, no wp d) 24lc024-i/p: industrial temperature, 2.5v, pdip package e) 24lc024-i/ms: industrial temperature, 2.5v, msop package, tape and reel f) 24lc025-t-i/sn: industrial temperature, 2.5v, soic package, tape and reel, no wp
24aa024/24lc024/24AA025/24lc025 ds21210g-page 20 ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. ds21210g-page 21 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. no representation or warranty is given and no liability is assumed by microchip technol ogy incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of micr ochip?s products as critical components in life support syst ems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or ot herwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, mxdev, mxlab, picmaster, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, migratable memory, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, rflab, rfpicdem, select mode, smart serial, smarttel and total endurance ar e trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2004, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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